Page Archive

[2020-07-12]Challenging Sequential Bitstream Processing via Principled Bitwise Speculation

Published: July 12, 2020

[2020-07-13]Orbital Edge Computing: Nanosatellite Constellations as a New Class of Computing System

Published: July 13, 2020

[2020-07-15]Coterie: Exploiting Frame Similarity to Enable High-Quality Multiplayer VR on Commodity Mobile Devices

Published: July 15, 2020

[2020-07-16]Wild and Crazy Ideas (ASPLOS 2020)

Published: July 16, 2020

[2020-07-20]Optimus Prime: Accelerating Data Transformation in Servers

Published: July 20, 2020

[2020-07-26]High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs

Published: July 26, 2020

[2020-11-14] High-Performance Deep-Learning Coprocessor Integrated into x86 SoC with Server-Class CPUs

Published: November 14, 2020

[2021-01-07] Echo: Compiler-based GPU Memory Footprint Reduction for LSTM RNN Training

Published: January 07, 2021

[2021-01-11] [CS224W] Properties of Networks and Random Graph Models

Published: January 11, 2021

[2021-01-12] [CS224W] Motifs and Structural Roles in Networks

Published: January 12, 2021

[2021-01-13] [CS224W] Community Structure in Networks

Published: January 13, 2021

[2021-01-15] [CS224W] Spectral Clustering

Published: January 15, 2021

[2021-01-17] [CS224W] Graph Repesentation Learning

Published: January 17, 2021

[2021-01-18] [CS224W] Graph Neural Network

Published: January 18, 2021

[2021-01-26] GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms

Published: January 26, 2021

[2021-02-20] Analyzing and Mitigating Data Stalls in DNN Training

Published: February 20, 2021

[2021-04-20] DiAG: A Dataflow-Inspired Architecture for General-Purpose Processors

Published: April 20, 2021

[2021-09-24] Ten Lessons From Three Generations Shaped Google’s TPUv4i : Industrial Product

Published: September 24, 2021

[2021-10-12] ISCA 2021 Section 3A: Machine Learning 1

Published: October 12, 2021

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BitSET: Bit-Serial Early Termination for Computation Reduction in Convolutional Neural Networks

A software-hardware co-design to accelerate DNNs

Out of Order CPU

Risc V 4-way Superscalar R10K OoO Processor

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