Out of Order CPU
Out-of-order pipelining is widely used in high-performance processors to avoid some kinds of stalls thatdecreasing CPI. Our work designs a 4-way Superscalar Out-of-Order Processor in SystemVerilog imple-mented by Group 8 OoO for EECS 470 final project. Our goal is to design a core with several advancedfeatures and high performance while maintaining correctness. Our design includes the following features: graphical debugging Tool, store-to-load forwarding in LSQ, post-retirement store buffer, multiple outstanding load misses, return address stack, vitcim cache, etc.