[2021-04-20] DiAG: A Dataflow-Inspired Architecture for General-Purpose Processors

less than 1 minute read

Published: April 20, 2021

In my point of view, it is basically a spatial dataflow architecture with more general compatiblity.

Difference from dataflow architecture

instructions are assigned in program order, but execute out-of-order
use register lanes instead of register file to contruct a dataflow graph and serve as a reorder buffer
PEs are chained rather than a 2D array

Dataflow in DiAG architecture

Pros and Cons

Dynamic datapaths constructed by DiAG are reusable, thus loop iterations can execute at an efficiency close to accelerators
On the other hand, applications that are memory-centric or contain significant control divergence perform poorly since most cycles are wasted on stalls
area overhead

My questions

Why CGRA could not be a main processor, but only be a co-processors?

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[2021-10-12] ISCA 2021 Section 3A: Machine Learning 1

1 minute read

Published: October 12, 2021

This reading blog is about three papers in Section 3A: Machine Learning 1 of ISCA 2021.

RaPiD: AI Accelerator for Ultra-Low Precision Training and Inference

This accelerator supports mixed precisions for both training and inference: 16 and 8-bit floating-point and 4 and 2-bit fixed point. It imporves both performance(TOPS) and energy efficiency(TOPS/W) at ultra-low preceision. In my opinion, this work contributes more on the engineering part (architecture).

[2021-09-24] Ten Lessons From Three Generations Shaped Google’s TPUv4i : Industrial Product

2 minute read

Published: September 24, 2021

I was quite busy during this year’s ISCA, so I did not have the chance to read the papers or watch the videos carefully. I will try to read the ISCA 2021 papers that I am interested in, hopefull before MICRO 2021 starts.

[2021-02-20] Analyzing and Mitigating Data Stalls in DNN Training

3 minute read

Published: February 20, 2021

Most DNN acclerator papers I read focus on DNN inference rather than training. From this paper, I learned that the bottleneck for DNN training is I/O for fetching data and CPU side for preprocessing.

Background

[2021-01-26] GraphACT: Accelerating GCN Training on CPU-FPGA Heterogeneous Platforms

1 minute read

Published: January 26, 2021

This paper is a CPU-FPGA heterogenrous platform for GCN training. CPU will do the communication intensive operations, and leave the computation intensive parts to CPU.

Background and Motivation

It is challenging to accelerate Graph Convolutional Networks because: (1) substantial and irregular data communication to propagate information within the graph (2) intensive computation to propagate information along the neural network layers (3) Degree-imbalance ofgraph nodes can significantly degrade the performance of feature propagation.

Yunjie Pan